As dimensions of integrated circuits are reduced, numerous challenges to manufacturing are presented. One such challenge is the patterning of features (e.g., channels, gate stacks, spacers, etc.) that are smaller than those achievable with a single mask. To achieve integrated circuit (IC) features that are closer together than currently possible with one mask, a layout is split into at least a first mask and a second mask. The first mask is used to form a first set of features defined in the layout, and the second mask is used to form a second set of features defined in the layout. This process is referred to as multiple patterning technology (MPT). MPT is used to form features on advanced technology nodes.
One drawback of MPT is the relatively high cost incurred by modifications to the layout. In some instances, designers include spare cells, or non-functional features in unused areas of the layout when designing ICs. Customers, managers, or other engineers may submit an Engineering Change Order (ECO), which is a request that the designed IC have different features, perform different functions, or be modified in some other way. When responding to an ECO, the designer can simply re-route lines or other connecting structures to the spare cell in order to make the requested change, if the spare cell fulfills the need of the ECO.
However, if a change must be made to a layer of the IC formed by MPT, the change often involves modifying two or more masks instead of a single mask. The modification of additional masks presents a higher level of difficulty and increases production time and costs in comparison with modifications to a single mask.